000			04221nam a22006015i 4500
001			978-3-319-42037-0
003			DE-He213
005			20210118121657.0
007			cr nn 008mamaa
008			160729s2017 gw | s |||| 0|eng d
020			_a9783319420370 _9978-3-319-42037-0
024	7		_a10.1007/978-3-319-42037-0 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
072		7	_aTJFC _2thema
082	0	4	_a621.3815 _223
100	1		_aLourenço, Nuno. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
245	1	0	_aAutomatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects _h[electronic resource] / _cby Nuno Lourenço, Ricardo Martins, Nuno Horta.
250			_a1st ed. 2017.
264		1	_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2017.
300			_aXXVII, 182 p. 112 illus., 90 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aIntroduction -- Previous Works on Automatic Analog IC Sizing -- AIDA-C Architecture -- Multi-Objective Optimization Kernel -- AIDA-C Circuit Sizing Results -- Layout-Aware Circuit Sizing -- AIDA-C Layout-aware Circuit Sizing Results -- Conclusions.
520			_aThis book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit’s performance. The discussion also includes robust circuit design and optimization and the most recent advances in layout-aware analog sizing approaches. The authors describe a methodology for an automatic flow for analog IC design, including details of the inputs and interfaces, multi-objective optimization techniques, and the enhancements made in the base implementation by using machine leaning techniques. The Gradient model is discussed in detail, along with the methods to include layout effects in the circuit sizing. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. An extensive set of application examples is included to demonstrate the capabilities and features of the methodologies described.
650		0	_aElectronic circuits.
650		0	_aMicroprocessors.
650		0	_aElectronics.
650		0	_aMicroelectronics.
650	1	4	_aCircuits and Systems. _0http://scigraph.springernature.com/things/product-market-codes/T24068
650	2	4	_aProcessor Architectures. _0http://scigraph.springernature.com/things/product-market-codes/I13014
650	2	4	_aElectronics and Microelectronics, Instrumentation. _0http://scigraph.springernature.com/things/product-market-codes/T24027
700	1		_aMartins, Ricardo. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
700	1		_aHorta, Nuno. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9783319420363
776	0	8	_iPrinted edition: _z9783319420387
776	0	8	_iPrinted edition: _z9783319824857
856	4	0	_uhttps://doi.org/10.1007/978-3-319-42037-0
912			_aZDB-2-ENG
999			_c445269 _d445269
942			_cEB
506			_aAvailable to subscribing member institutions only. Доступно лише організаціям членам підписки.
506			_fOnline access from local network of NaUOA.
506			_fOnline access with authorization at https://link.springer.com/
506			_fОнлайн-доступ з локальної мережі НаУОА.
506			_fОнлайн доступ з авторизацією на https://link.springer.com/