000			04218nam a22006015i 4500
001			978-3-319-34060-9
003			DE-He213
005			20210118124321.0
007			cr nn 008mamaa
008			160720s2017 gw | s |||| 0|eng d
020			_a9783319340609 _9978-3-319-34060-9
024	7		_a10.1007/978-3-319-34060-9 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
072		7	_aTJFC _2thema
082	0	4	_a621.3815 _223
100	1		_aMartins, Ricardo. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
245	1	0	_aAnalog Integrated Circuit Design Automation _h[electronic resource] : _bPlacement, Routing and Parasitic Extraction Techniques / _cby Ricardo Martins, Nuno Lourenço, Nuno Horta.
250			_a1st ed. 2017.
264		1	_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2017.
300			_aXVI, 207 p. 108 illus., 79 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_a1 Introduction -- 2 State-of-the-Art on Analog Layout Automation -- 3 AIDA-L: Architecture and Integration -- 4 Template-based Placer -- 5 Optimization-based Placer -- 6 Fully-Automatic Router -- 7 Empirical-based Parasitic Extractor -- 8 Experimental Results -- 9 Conclusions and Future Work.
520			_aThis book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets. Introduces readers to hierarchical combination of Pareto fronts of placements; Presents electromigration-aware routing with multilayer multiport terminal structures; Includes evolutionary multi-objective multi-constraint detailed Router; Enables parasitic extraction performed over a semi-complete layout.
650		0	_aElectronic circuits.
650		0	_aMicroprocessors.
650		0	_aElectronics.
650		0	_aMicroelectronics.
650	1	4	_aCircuits and Systems. _0http://scigraph.springernature.com/things/product-market-codes/T24068
650	2	4	_aProcessor Architectures. _0http://scigraph.springernature.com/things/product-market-codes/I13014
650	2	4	_aElectronics and Microelectronics, Instrumentation. _0http://scigraph.springernature.com/things/product-market-codes/T24027
700	1		_aLourenço, Nuno. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
700	1		_aHorta, Nuno. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9783319340593
776	0	8	_iPrinted edition: _z9783319340616
776	0	8	_iPrinted edition: _z9783319816685
856	4	0	_uhttps://doi.org/10.1007/978-3-319-34060-9
912			_aZDB-2-ENG
999			_c446486 _d446486
942			_cEB
506			_aAvailable to subscribing member institutions only. Доступно лише організаціям членам підписки.
506			_fOnline access from local network of NaUOA.
506			_fOnline access with authorization at https://link.springer.com/
506			_fОнлайн-доступ з локальної мережі НаУОА.
506			_fОнлайн доступ з авторизацією на https://link.springer.com/